Speeding deSign of CuStom S il iCon

AbStRACt As the industry migrates to more advanced manufacturing technologies, growing complexity in custom integrated circuit (iC) design threatens to increase delays and dramatically boost the cost of differentiated custom silicon. for semiconductor companies, achieving success in the face of these emerging technical and market challenges rests squarely on their ability to improve the efficiency of custom iC development— from design through layout and verification and into manufacturing. by combining new techniques such as constraint management and advanced interoperability technologies within a unified design environment , new design platforms promise to meet these growing challenges across the full breadth of analog/ mixed-signal design—from mainstream analog iCs at 130nm and above to advanced cell characterization at 45nm and below. the Cadence ® Virtuoso ® custom design platform leverages advances in design methods, user-interface technologies and data infrastructure standards to help analog, mixed-signal and radio-frequency (Rf) design teams deliver differentiated, high-quality custom silicon on time.